Name
Abstract | ||
|---|---|---|
This work proposes a 14b 100MS/s 0.18mum CMOS ADC for the fourth-generation mobile communication systems. The proposed 3-stage pipeline ADC, whose architecture is verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b sub-ranging flash ADC based on open-loop offset sampling and interpolation to obtain a small chip area at 6b. The prototype ADC implemented in a 0.18mum CMOS technology demonstrates the measured DNL and INL within 1.03LSB and 5.47LSB, respectively, while the ADC shows an SNDR of 59dB and an SFDR of 72dB with an active die area of 3.4mm2 and a power consumption of 145mW at 100MS/s and 1.8V |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/APCCAS.2006.342442 | APCCAS |
Keywords | Field | DocType |
mobile communication systems,cmos integrated circuits,capacitor mismatch,high resolution,analogue-digital conversion,integrated circuit modelling,low noise amplifiers,low noise amplifier,pipeline,3-d symmetric layout,behavioral model simulations,enob,adc,1.8 v,a/d converter,wide band amplifier,wideband amplifiers,cmos pipeline,3d fully symmetric layout,145 mw,sample and hold amplifier,mdac,cmos,sample and hold circuits,0.18 micron,nyquist input frequency,chip,behavior modeling | Low-noise amplifier,Capacitor,Computer science,Interpolation,Spurious-free dynamic range,Chip,Flash ADC,Electronic engineering,Effective number of bits,CMOS | Conference |
ISBN | Citations | PageRank |
1-4244-0387-1 | 0 | 0.34 |
References | Authors | |
1 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung-Hoon Lee | 1 | 71 | 15.77 |
| Young-jae Cho | 2 | 31 | 5.99 |
| Hee-Cheol Choi | 3 | 26 | 10.68 |
| Yong-hyun Park | 4 | 0 | 0.34 |
| Doo-hwan Sa | 5 | 5 | 1.26 |
| Young-Lok Kim | 6 | 17 | 4.26 |
| Seunghoon Lee | 7 | 244 | 61.57 |