Paper Info
Title
Assessing carbon nanotube bundle interconnect for future FPGA architectures
Abstract
Field Programmable Gate Arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process technology continues to scale, standard copper interconnect will become a major bottleneck for FPGA performance. In this paper, we propose utilizing bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric and compare their performance to standard copper interconnect in future process technologies. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the segmentation distribution and the internal population of the wires. The results demonstrate that FPGAs utilizing SWCNT bundle interconnect can achieve a 19% improvement in average area delay product over the best performing architecture for standard copper interconnect in 22 nm process technology.
Year
DOI
Venue
2007
10.1109/DATE.2007.364609
DATE
Keywords
Field
DocType
future fpga architecture,fpgas utilizing swcnt bundle,standard copper,cmos process technology,fpga routing architecture,future process technology,performance advantage,assessing carbon nanotube bundle,important aspect,nm process technology,important hardware platform,fpga performance,copper,carbon nanotubes,network routing,system on a chip,routing,field programmable gate arrays,carbon nanotube,hardware,cmos technology,field programmable gate array
Population,Bottleneck,System on a chip,Computer science,Parallel computing,Field-programmable gate array,CMOS,Copper interconnect,Electronic engineering,Interconnection,Bundle,Embedded system
Conference
ISSN
ISBN
Citations 
1530-1591
978-3-9810801-2-4
19
PageRank 
References 
Authors
1.00
8
5
Name
Order
Citations
PageRank
S. Eachempati135815.79
Arthur Nieuwoudt220720.59
Aman Gayasen317610.35
Narayanan Vijaykrishnan46955524.60
Yehia Massoud5772113.05