Paper Info
Title
Verify level control criteria for multi-level cell flash memories and their applications.
Abstract
In 1M-bit/cell multi-level cell (MLC) flash memories, it is more difficult to guarantee the reliability of data as M increases. The reason is that an M-bit/cell MLC has 2 M states whereas a single-level cell (SLC) has only two states. Hence, compared to SLC, the margin of MLC is reduced, thereby making it sensitive to a number of degradation mechanisms such as cell-to-cell interference and charge leakage. In flash memories, distances between 2 M states can be controlled by adjusting verify levels during incremental step pulse programming (ISPP). For high data reliability, the control of verify levels in ISPP is important because the bit error rate (BER) will be affected significantly by verify levels. As M increases, the verify level control will be more important and complex. In this article, we investigate two verify level control criteria for MLC flash memories. The first criterion is to minimize the overall BER and the second criterion is to make page BERs equal. The choice between these criteria relates to flash memory architecture, bits per cell, reliability, and speed performance. Considering these factors, we will discuss the strategy of verify level control in the hybrid solid state drives (SSD) which are composed of flash memories with different number of bits per cell.
Year
DOI
Venue
2012
10.1186/1687-6180-2012-196
EURASIP J. Adv. Sig. Proc.
Keywords
Field
DocType
Speed Performance, Flash Memory, Word Error Rate, Phase Change Memory, Solid State Drive
Multi-level cell,Phase-change memory,Flash memory,Leakage (electronics),Computer science,Word error rate,Interference (wave propagation),Solid-state drive,Computer hardware,Bit error rate
Journal
Volume
Issue
ISSN
2012
1
1687-6180
Citations 
PageRank 
References 
10
0.58
9
Authors
5
Name
Order
Citations
PageRank
Yongjune Kim1548.76
Jaehong Kim2100.92
Jun Jin Kong3515.83
B. V. K. Vijaya Kumar4924126.77
Xin Li570948.36