Title
A 19 nm 112.8 mm 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
Abstract
A 64 Gb MLC NAND flash memory in 19 nm CMOS technology has been developed. By adopting one-sided all bit line (ABL) architecture, the single cell array configuration, bit line bias acceleration (BLBA) and BC states first program algorithm, the smallest 64 Gb die size in 2 bit/cell is achieved with high performance of 15 MB/s program throughput. Program suspend and erase suspend functions are introduced to improve the read latency. High speed toggle mode interface of 400 Mbit/sec/pin at VCCQ = 1.8 V is also realized.
Year
DOI
Venue
2013
10.1109/JSSC.2012.2215094
IEEE Journal of Solid-state Circuits
Keywords
DocType
Volume
single cell array configuration,resume,program suspend functions,ABL architecture,bit line bias acceleration,NAND flash memory,suspend,bit rate 15 Mbit/s,voltage 1.8 V,high-speed interface,erase suspend functions,size 19 nm,CMOS technology,cell-to-cell coupling effect,one-sided all bit line architecture,read latency,BLBA,multilevel flash memory,CMOS digital integrated circuits,program throughput,all bit line(ABL) architecture,MLC NAND flash memory,Vth distribution,flash memories,toggle mode interface,BC state first program
Journal
48
Issue
ISSN
Citations 
1
0018-9200
2
PageRank 
References 
Authors
0.44
0
32