Name
Abstract | ||
|---|---|---|
Combining ideas from several previous proposals, such as Active Pages, DIVA, and ULMT, we present the Memory Arithmetic Unit and Interface (MAUI) architecture. Because the "intelligence" of the MAUI intelligent memory system architecture is located in the memory-controller, logic and DRAM are not required to be integrated into a single chip, and use of off-the-shelf DRAMs is permitted. The MAUI's computational engine performs memory-bound SIMD computations close to the memory system, enabling more efficient memory pipelining. A simulator modeling the MAUI architecture was added to the SimpleScalar v4.0 tool-set. Not surprisingly, simulations show that application speedup increases as the memory system speed increases and the dataset size increases. Simulation results show single-threaded application speedup of over 100% is possible, and suggest that a total system speedup of about 300% is possible in a multi-threaded environment. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1111583.1111590 | Memory System Performance |
Keywords | Field | DocType |
combining idea,active pages,memory system,maui architecture,memory system speed increase,efficient memory pipelining,maui intelligent memory system,single-threaded application speedup,performance characteristic,total system speedup,application speedup increase,intelligent memory system architecture,simulation model,vector processing,chip | Registered memory,Interleaved memory,Uniform memory access,Shared memory,Computer science,Parallel computing,Cache-only memory architecture,Memory map,Memory architecture,Memory controller | Conference |
ISBN | Citations | PageRank |
1-59593-147-3 | 1 | 0.35 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Justin Teller | 1 | 49 | 3.15 |
| Charles B. Silio, Jr. | 2 | 7 | 2.45 |
| Bruce Jacob | 3 | 1543 | 103.58 |