Paper Info
Title
DVB-DSNG modem high level synthesis in an optimized latency insensitive system context
Abstract
This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al.. This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists in IP encapsulation into a new wrapper model containing a synchronization processor which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT [1], a high-level synthesis tool.
Year
DOI
Venue
2005
10.1007/11512622_45
SAMOS
Keywords
Field
DocType
ips intensive reuse,synchronization processor,intensive digital signal processing,design automation,ip encapsulation,new wrapper model,soc design methodology,optimized latency insensitive system,local ip performance,dvb-dsng modem high level,synchronization wrapper,rnrt alipta project,high level synthesis,digital signal processing,critical path,design methodology
Digital signal processing,Synchronization,System on a chip,Computer science,Digital signal,High-level synthesis,Electronic design automation,Digital Video Broadcasting,Critical path method,Embedded system
Conference
Volume
ISSN
ISBN
3553
0302-9743
3-540-26969-X
Citations 
PageRank 
References 
0
0.34
10
Authors
6
Name
Order
Citations
PageRank
P. Bomel121.77
N. Abdelli200.34
E. Martin300.34
A-M. Fouilliart400.68
E. Boutillon5203.37
P. Kajfasz600.34