Name
Abstract | ||
|---|---|---|
In this paper, we propose an efficient low-complexity switch network design for reconfigurable low-density parity-check (LDPC) decoders. The proposed architecture leads to significant reductions in hardware complexity. Since the structured quasi-cyclic (QC) LDPC codes for most modern wireless communication systems include multiple code rates, various block lengths, and different sizes of submatrices, a reconfigurable LDPC decoder is desirable and the barrel shifter needs to be programmable. The Benes network cannot be optimized as the barrel shifter for a reconfigurable LDPC decoder when the input size of barrel shifter is not a power of 2. Also, it is not trivial to generate all the control signals on-the-fly for numerous 2 × 2 switches in the switch network. In this paper, a novel low-complexity switch network design is proposed, which can be used efficiently when the input size of barrel shifters is not a power of 2. Furthermore, we propose a novel algorithm to generate all the control signals, which can be implemented with a small size of lookup table (LUT) or a simple combination logic on-the-fly, using the properties that both the full-size switch network can be broken into two half-size switch networks and the barrel shifters for the structured QC LDPC decoders require only cyclic shifts. Compared with conventional Benes networks using a dedicated LUT or a complicated signal generating algorithm, the proposed architectures achieve significant hardware reductions in implementing the barrel shifters for reconfigurable LDPC decoders. In synthesis result using the TSMC 0.18-µm standard cell CMOS technology, the proposed switch network for a reconfigurable LDPC decoder of IEEE 802.16e and IEEE 802.11n can be implemented with an area of 0.772 mm2, which leads to a significant area reduction. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TVLSI.2008.2007736 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
input size,barrel shifter,benes network,low-complexity switch network,conventional benes network,reconfigurable ldpc decoder,efficient low-complexity switch network,structured qc ldpc decoder,ldpc code,barrel shifters,proposed architecture,wireless communication,vlsi,decoding,generic algorithm,cmos technology,low density parity check,switch network,signal generators,switches,communication complexity,lookup table,hardware | Lookup table,Circuit complexity,Computer science,Low-density parity-check code,Barrel shifter,Electronic engineering,Real-time computing,Communication complexity,Network switch,Standard cell,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
18 | 1 | 1063-8210 |
Citations | PageRank | References |
22 | 1.01 | 10 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daesun Oh | 1 | 74 | 5.54 |
| keshab k parhi | 2 | 3235 | 369.07 |