Name
Abstract | ||
|---|---|---|
A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0.18um standard CMOS process is described. The typical (8kx16) cut is achieving 300Mhz maximum frequency, with a 3.3ns access time at 1.3V and 25°C and a typical power of 60A/Mhz at 1.3V. Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture and a differential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder. The generator ranges from 1Kbit to 2Mbit and features an optional programmable redundancy. |
Year | Venue | Keywords |
|---|---|---|
2000 | MTDT | m Standard CMOS Process,access time,generator range,differential output bus,Single Port SRAM Generator,time high speed,typical power,novel dynamic wordline decoder,low power characteristic,maximum frequency,hierarchical wordline architecture,Low Voltage,SRAM memory generator |
DocType | ISBN | Citations |
Conference | 0-7695-0689-5 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Frey | 1 | 0 | 0.34 |
| F. Genevaux | 2 | 0 | 0.34 |
| C. Issartel | 3 | 0 | 0.34 |
| D. Turgis | 4 | 11 | 4.96 |
| Jp. Schoellkopf | 5 | 0 | 0.34 |