Title
On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks
Abstract
Side-channel attacks are a realistic threat to the security of real world implementations of cryptographic algorithms. In order to evaluate the resistance of designs against power analysis attacks, power values obtained from circuit simulations in early design phases offer two distinct advantages: First, they offer fast feedback loops to designers, second the number of redesigns can be reduced. This work investigates the accuracy of design time power estimation tools in assessing the security level of a device against differential power attacks.
Year
DOI
Venue
2011
10.1109/DSD.2011.103
DSD
Keywords
Field
DocType
distinct advantage,power attacks,fast feedback loop,security level,power analysis attack,differential power attack,design time evaluation,side-channel attack,design time power estimation,early design phase,circuit simulation,cryptographic algorithm,side channel attacks,cryptography,semiconductor devices,encryption,integrated circuit,power analysis,correlation
Power analysis,Security level,Computer science,Cryptography,Implementation,Real-time computing,Encryption,Side channel attack
Conference
Citations 
PageRank 
References 
3
0.42
3
Authors
4
Name
Order
Citations
PageRank
Alessandro Barenghi149946.79
Guido Bertoni269641.77
Fabrizio De Santis38410.44
Filippo Melzani4133.71