Name
Abstract | ||
|---|---|---|
In all stages of VLSI chip design, routing estimation is required to account for the effect of interconnects. We propose a fast Steiner tree construction algorithm, which is 3-180 times faster for 10-300 point Steiner trees, and within 2.5% of the length of the Batched-1-Steiner tree. The proposed method can be used as a fast net length estimation tool in VLSI CAD applications, e.g. in the inner cycle of a floorplanning/placement engine. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/764808.764858 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
novel ultra-fast heuristic,fast steiner tree construction,vlsi chip design,point steiner tree,vlsi cad application,placement engine,length estimation tool,vlsi cad steiner tree,batched-1-steiner tree,inner cycle,chip,routing,steiner trees,steiner tree | Heuristic,Vlsi cad,Steiner tree problem,Computer science,Parallel computing,Theoretical computer science,Electronic engineering,Vlsi chip design,Floorplan | Conference |
ISBN | Citations | PageRank |
1-58113-677-3 | 0 | 0.34 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Krishna A. Bharat | 1 | 1211 | 252.86 |
| C.Y. Roger Chen | 2 | 3 | 1.09 |
| Naresh K. Sehgal | 3 | 2 | 1.64 |