Name
Abstract | ||
|---|---|---|
This paper describes a new heuristic algorithm for the computation of tests to detect failures in sequential logic circuits. In the algorithm, the values of logic blocks in a logic circuit are expressed in boolean vectors with six elements and main process of the algorithm is the operations among these values. Presented in this paper are basic principles for the algorithm, their application procedure with an example and our experiences through the implemented system.
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Year | Venue | Keywords |
|---|---|---|
1974 | DAC | sequential logic circuit,sequential circuit,basic principle,new heuristic algorithm,logic block,main process,boolean vector,new heuristic test generation,application procedure,logic circuit,computer aided design,integrated circuit layout,sequential circuits,design automation,heuristic algorithm |
Field | DocType | Issue |
Logic synthesis,Digital electronics,Boolean circuit,Sequential logic,Algorithm design,Computer science,Logic optimization,Algorithm,Electronic engineering,Register-transfer level,Asynchronous circuit | Conference | 36 |
ISSN | ISBN | Citations |
0547-051X | 978-1-4503-7448-4 | 1 |
PageRank | References | Authors |
3.11 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshihiro Arima | 1 | 1 | 3.11 |
| Mitsukuni Tsuboya | 2 | 1 | 3.11 |
| Goro Amamiya | 3 | 5 | 7.18 |
| Jiro Okuda | 4 | 47 | 10.56 |