Paper Info
Title
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs
Abstract
This paper presents a modular verification approach for asynchronous circuits to address state explosion with a novel interface refinement method to reduce false counterexamples.This method borrows the idea of parallel composition, and it iteratively refines each component in a design by examining its interface interactions, and removes the behavior not synchronized with its neighbors. This method is further enhanced by synchronizing multiple components simultaneously so that inter-dependencies among components are considered. The experiments on several large asynchronous circuits show that this method efficiently removes impossible behavior from each component including ones violating correctness requirements.
Year
DOI
Venue
2009
10.1109/ISVLSI.2009.16
ISVLSI
Keywords
Field
DocType
multiple component,novel interface refinement method,logic cad,modular verification approach,interface interaction,learning (artificial intelligence),asynchronous design,asynchronous designs,asynchronous circuit,synchronization-based abstraction refinement,correctness requirement,large asynchronous circuit,impossible behavior,parallel composition,graph theory,asynchronous circuits,modular verification,iterative methods,false counterexamples,hazards,learning artificial intelligence,informatics,synchronization,artificial intelligence,data mining,cognition,probability density function,algorithm design and analysis,very large scale integration
Graph theory,Asynchronous communication,Synchronization,Iterative method,Computer science,Synchronizing,Correctness,Modular design,Electronic circuit,Distributed computing
Conference
ISSN
ISBN
Citations 
2159-3469
978-0-7695-3684-2
1
PageRank 
References 
Authors
0.36
8
3
Name
Order
Citations
PageRank
Hao Zheng19513.32
Haiqiong Yao2151.61
Tomohiro Yoneda335341.62