Name
Abstract | ||
|---|---|---|
The synthesis and mapping of applications to configurable embedded systems is a notoriously complex process. Design-flows typically include tools that have a wide range of parameters which interact in very unpredictable ways, thus creating a large and complex design space. When exploring this space, designers must manage the interfaces between different tools and apply, often manually, a sequence of tool-specific transformations making design exploration extremely cumbersome and error-prone. This paper describes the use of techniques inspired by aspect-oriented technology and scripting languages for defining and exploring hardware compilation strategies. In particular, our approach allows developers to control all stages of a hardware/software compilation and synthesis toolchain: from code transformations and compiler optimizations to placement and routing for tuning the performance of application kernels. Our approach takes advantage of an integrated framework which provides a transparent and unified view over toolchains, their data output and the control of their execution. We illustrate the use of our approach when designing application-specific hardware architectures generated by a toolchain composed of high-level source-code transformation and synthesis tools. The results show the impact of various strategies when targeting custom hardware and expose the complexities in devising these strategies, hence highlighting the productivity benefits of this approach. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1016/j.micpro.2013.06.001 | Microprocessors and Microsystems - Embedded Hardware Design |
Keywords | Field | DocType |
synthesis tool,lara aspect,software compilation,custom hardware,application kernel,complete hardware synthesis toolchain,application-specific hardware,design exploration,complex process,hardware compilation strategy,complex design space,synthesis toolchain,aspect oriented programming,fpgas | Computer architecture,Aspect-oriented programming,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Optimizing compiler,Software,Hardware synthesis,Toolchain,Hardware architecture,Scripting language | Journal |
Volume | Issue | ISSN |
37 | 8 | 0141-9331 |
Citations | PageRank | References |
9 | 0.56 | 15 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| João M. P. Cardoso | 1 | 462 | 57.24 |
| Tiago Carvalho | 2 | 41 | 7.98 |
| J. G. F. Coutinho | 3 | 125 | 17.26 |
| Ricardo Nobre | 4 | 97 | 10.09 |
| Razvan Nane | 5 | 35 | 6.35 |
| Pedro C. Diniz | 6 | 1061 | 85.47 |
| Zlatko Petrov | 7 | 125 | 7.51 |
| Wayne Luk | 8 | 3752 | 438.09 |
| Koen Bertels | 9 | 1365 | 138.66 |