Name
Abstract | ||
|---|---|---|
A 10-b, 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) converts from dc to the 12th Nyquist band with in situ, mostly digital background calibration for the clock skew in the 3.5-b front-end stage. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-desce... |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/JSSC.2011.2151510 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Calibration,Redundancy,Synchronization,Capacitors,Noise | Comparator,Dynamic range,Computer science,Electronic engineering,Spurious-free dynamic range,Clock skew,Skew,Electronic circuit,Calibration,Amplifier | Journal |
Volume | Issue | ISSN |
46 | 8 | 0018-9200 |
Citations | PageRank | References |
11 | 1.31 | 5 |
Authors | ||
12 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pingli Huang | 1 | 113 | 11.04 |
| Szukang Hsien | 2 | 20 | 4.88 |
| Victor Lu | 3 | 14 | 2.02 |
| Peiyuan Wan | 4 | 24 | 4.63 |
| Seung-Chul Lee | 5 | 124 | 18.27 |
| Wenbo Liu | 6 | 114 | 12.15 |
| Bo-Wei Chen | 7 | 262 | 30.12 |
| Yung-Pin Lee | 8 | 100 | 17.18 |
| Wen-Tsao Chen | 9 | 31 | 7.62 |
| Tzu-Yi Yang | 10 | 77 | 12.45 |
| Gin-Kou Ma | 11 | 140 | 22.51 |
| Yun Chiu | 12 | 241 | 32.85 |