Name
Abstract | ||
|---|---|---|
The hybrid delay scan design in which some flip flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed. Noticing that the hybrid delay scan design potentially has a capability of two test application modes: one is the broad-side test mode, and the other is the hybrid test mode, we present a hybrid test application of the two test modes in the hybrid delay scan design. In addition, we also address a way of skewed-load FF selection based on propagation dominance of FFs in order to take advantage of the hybrid test application. Experimental results for ITC'99 benchmark circuits show that the proposed hybrid scan design with the hybrid test application can achieve higher fault coverage than the previous hybrid scan design. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ETSYM.2010.5512744 | European Test Symposium |
Keywords | Field | DocType |
integrated circuit testing,benchmark circuits,hybrid delay scan design,skewed load flip flops,hybrid test application,hybrid test mode,logic design,broadside test mode,flip-flops,logic testing,logic gates,benchmark testing,hardware,fault coverage,error correction,controllability,fault detection | Logic synthesis,Logic gate,Controllability,Fault coverage,Logic testing,Computer science,Electronic engineering,Real-time computing,Electronic circuit,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
1530-1877 E-ISBN : 978-1-4244-5833-2 | 978-1-4244-5833-2 | 0 |
PageRank | References | Authors |
0.34 | 1 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuki Yoshikawa | 1 | 28 | 4.51 |
| Tomomi Nuwa | 2 | 0 | 0.68 |
| Hideyuki Ichihara | 3 | 96 | 18.92 |
| Tomoo Inoue | 4 | 352 | 47.23 |