Name
Title | ||
|---|---|---|
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system |
Abstract | ||
|---|---|---|
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc=3.3 V and T=25°C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/4.726563 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
DRAM chips,delay circuits,memory architecture,25 degC,256 MByte,3.3 V,40 mW,40 to 160 MHz,64 Mbit,640 MByte/s,DLL,access time,bidirectional data strobed device,chip-size overhead,double-data-rate SDRAM,locking frequency,minimized loading difference,prefetch operation,twisted data bussing architecture | Journal | 33 |
Issue | ISSN | Citations |
11 | 0018-9200 | 15 |
PageRank | References | Authors |
4.72 | 1 | 15 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. H. Kim | 1 | 15 | 4.72 |
| J. Lee | 2 | 101 | 16.30 |
| J. B. Lee | 3 | 19 | 5.20 |
| B. S. Kim | 4 | 47 | 12.43 |
| C. S. Park | 5 | 15 | 4.72 |
| Lee, B.S. | 6 | 32 | 15.65 |
| S. Y. Lee | 7 | 35 | 7.84 |
| C. W. Park | 8 | 21 | 5.97 |
| J. G. Roh | 9 | 15 | 4.72 |
| Hyo Suk Nam | 10 | 25 | 7.41 |
| D. Y. Kim | 11 | 49 | 8.75 |
| D. Y. Lee | 12 | 27 | 6.97 |
| T. S. Jung | 13 | 18 | 5.14 |
| H. Yoon | 14 | 15 | 4.72 |
| S. I. Cho | 15 | 20 | 5.69 |