Name
Abstract | ||
|---|---|---|
Since the announcement of the development of a technique for using MOS transistor integrated circuits as associative memory cells, 128 words of 48 bits per word associative memory has been experimented and engineered. |
Year | DOI | Venue |
|---|---|---|
1967 | 10.1145/1465482.1465565 | AFIPS Spring Joint Computing Conference |
Keywords | Field | DocType |
memory system,associative memory cell,ns cycle time,mos transistor integrated circuit,word associative memory,integrated mos transistor associative,associative memory,integrated circuit,cycle time | Dynamic random-access memory,Registered memory,Semiconductor memory,Content-addressable memory,Non-volatile random-access memory,Computer science,Transistor,Computer hardware,Computer memory,Memory refresh | Conference |
Citations | PageRank | References |
1 | 0.37 | 1 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ryo Igarashi | 1 | 6 | 1.63 |
| Toru Yaita | 2 | 1 | 0.37 |