Name
Title | ||
|---|---|---|
Design and FPGA implementation of an embedded real-time biologically plausible spiking neural network processor |
Abstract | ||
|---|---|---|
The implementation of a large scale, leaky-integrate-and-fire neural network processor using the Xilinx Virtex-II family of field programmable gate array (FPGA) is presented. The processor has been designed to model biologically plausible networks of spiking neurons in real-time to assist with the control of a mobile robot. The real-time constraint has led to a re-evaluation of some of the established architectural and algorithmic features of previous spiking neural network based hardware. The design was coded and simulated using Handel-C hardware description language (HDL) and the DK3 design suite from Celoxica. The processor has been physically implemented and tested on a RC200 development board, also from Celoxica. |
Year | DOI | Keywords |
|---|---|---|
2005 | 10.1109/FPL.2005.1515790 | embedded systems,field programmable gate arrays,microprocessor chips,mobile robots,neural nets,DK3 design suite,FPGA implementation,Handel-C hardware description language,RC200 development board,Xilinx Virtex-II,biologically plausible networks,leaky-integrate-and-fire neural network processor,mobile robot,spiking neural network processor,spiking neurons |
Field | DocType | ISBN |
Suite,Computer science,Field-programmable gate array,Real-time computing,Spiking neural network,Artificial neural network,Mobile robot,Hardware description language | Conference | 0-7803-9362-7 |
Citations | PageRank | References |
6 | 0.63 | 3 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin J. Pearson | 1 | 215 | 26.34 |
| Chris Melhuish | 2 | 747 | 87.61 |
| Anthony G. Pipe | 3 | 255 | 39.08 |
| Mokhtar Nibouche | 4 | 50 | 11.87 |
| Ian Gilhespy | 5 | 75 | 10.01 |
| Kevin N. Gurney | 6 | 445 | 53.49 |
| Benjamin Mitchinson | 7 | 86 | 7.90 |