Name
Abstract | ||
|---|---|---|
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with LRU replacement policies to combine fast access with relatively low miss rates. To improve replacement decisions in set-associative caches, we develop a new set of compiler algorithms that predict which data will and will not be reused and provide these hints to the architecture. We prove that the hints either match or improve hit rates over LRU. We describe a practical one-bit cache-line tag implementation of our algorithm, called evict-me. On a cache replacement, the architecture will replace a line for which the evict-me bit is set, or if none is set, it will use the LRU bits. We implement our compiler analysis and its output in the Scale compiler. On a variety of scientific programs, using the evict-me algorithm in both the level 1 and 2 caches improves simulated cycle times by up to 34% over the LRU policy by increasing hit rates. In addition, a combination of simple hardware prefetching and evict-me works together to further improve performance. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/PACT.2002.1106018 | IEEE PACT |
Keywords | Field | DocType |
lru replacement policies,compiler algorithm,scale compiler,cache storage,storage management,improve cache replacement decisions,evict-me,evict-me bit,cache replacement,lru replacement policy,scientific programs,microprocessor performance,hardware prefetching,program compiler,memory performance,set-associative cache,compiler analysis,performance evaluation,content-addressable storage,hit rates,one-bit cache-line tag implementation,lru policy,evict-me algorithm,lru bit,cache replacement decisions,program compilers,prediction algorithms,embedded processor,instruction scheduling,computer science,cycle time,computer architecture,hardware,microarchitecture,enumeration,dictionary | Architecture,Instruction scheduling,Cache,Computer science,Parallel computing,Microprocessor,Real-time computing,Compiler,Content-addressable storage,Adaptive replacement cache,Operating system,Microarchitecture | Conference |
ISSN | ISBN | Citations |
1089-795X | 0-7695-1620-3 | 60 |
PageRank | References | Authors |
6.52 | 24 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhenlin Wang | 1 | 66 | 6.96 |
| Kathryn S. Mckinley | 2 | 3746 | 267.74 |
| Arnold L. Rosenberg | 3 | 2107 | 640.21 |
| charles c weems | 4 | 176 | 27.78 |