Title
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
Abstract
We propose a parametrized memory template for applications with parallel for loops. The template's parameters reflect important trade-offs made during system design. The template is incorporated in our high level synthesis (HLS) compiler, where the template's parameters are adjusted to the application. The template fits parallel for loops with no loop dependencies and sequential bodies. We found two alternative template implementations using our compiler. In the future, we will develop templates for other types of for loops. These will be added to the compiler and it will identify the template that works best for the application it is compiling. Once a template is selected, the compiler will use design space exploration to select the best combination of template parameters for the targeted hardware and application.
Year
DOI
Venue
2010
10.1109/DSD.2010.62
Digital System Design: Architectures, Methods and Tools
Keywords
Field
DocType
parametrized memory template,high level synthesis compiler,loop memory template,design space exploration,template parameter,important trade-offs,sequential body,system design,high level synthesis,loop dependency,best combination,alternative template,hardware,fpga,parallel,memory,template,compiler,vhdl,memory management,field programmable gate arrays,loop
Computer science,Template metaprogramming,High-level synthesis,Parallel computing,Loop optimization,Real-time computing,Compiler,Memory management,Template,Design space exploration,For loop
Conference
ISBN
Citations 
PageRank 
978-1-4244-7839-2
0
0.34
References 
Authors
6
4
Name
Order
Citations
PageRank
Craig Moore182.04
Wim Meeus2655.61
Harald Devos3347.10
dirk stroobandt4833101.36