Title
Automatic Defect Classification System In Semiconductors Eds Test Based On System Entity Structure Methodology
Abstract
We exploit a structural knowledge representation scheme called System Entity Structure (SES) methodology to represent and manage wafer failure patterns which can make a significant influence to FABs in the semiconductor industry. It is important for the engineers to simulate various system verification processes by using predefined system entities (e.g., decomposition, taxonomy, and coupling relationships of a system) contained in the SES. For better computational performance, given a certain failure pattern, a Pruned SES (PES) can be extracted by selecting the only relevant system entities from the SES. Therefore, the SES-based simulation system allows the engineers to efficiently evaluate and monitor semiconductor data by i) analyzing failures to find out the corresponding causes and ii) managing historical data related to such failures.
Year
DOI
Venue
2010
10.1587/transinf.E93.D.2001
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS
Keywords
Field
DocType
semiconductor, system entity structure, electrical die sorting, fail bit map data, pruning
Data mining,Knowledge representation and reasoning,Simulation system,Computer science,Exploit,Artificial intelligence,Semiconductor industry,Machine learning,System verification
Journal
Volume
Issue
ISSN
E93D
7
0916-8532
Citations 
PageRank 
References 
1
0.38
2
Authors
4
Name
Order
Citations
PageRank
Youngshin Han1278.28
Soyoung Kim216822.15
Taekyu Kim3144.89
Jason J. Jung41451135.51