Name
Title | ||
|---|---|---|
Description of a fault tolerance system implemented in a hardware architecture with self-adaptive capabilities |
Abstract | ||
|---|---|---|
This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way selfadaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1007/978-3-642-21498-1_70 | IWANN (2) |
Keywords | Field | DocType |
programmable configuration mode,self-adaptive capability,selfadaptive capability,runtime self-configuration,configurable multiprocessor,fault tolerance system,future implementation,data memory,new self-adaptive hardware architecture,self-replication capability,mimd,self replication,fault tolerance | Architecture,Computer architecture,Computer science,Software fault tolerance,Implementation,Multiprocessing,Fault tolerance,Self-replication,MIMD,Hardware architecture | Conference |
Volume | ISSN | Citations |
6692 | 0302-9743 | 1 |
PageRank | References | Authors |
0.36 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Javier Soto | 1 | 3 | 0.73 |
| Juan Manuel Moreno | 2 | 186 | 32.74 |
| joan cabestany | 3 | 1276 | 143.82 |