Name
Abstract | ||
|---|---|---|
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacity. Similar to prior work, EINIC integrates a redesigned NIC onto a CPU. However, we extend the integrated NIC (INIC) to multicore platforms and examine its behaviors with the network receiving optimization. Additionally, by exploiting NICs proximity to CPUs, we also design an I/O-aware last level shared cache (LLC). Our I/O-aware design allows us to split the cache into an I/O cache and a general cache in a flexible way. It ameliorates cache interferences between network and non-network data. Our simulation results show that EINIC not only attacks the mismatch, but also ameliorates the cache interference. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1882486.1882503 | ANCS |
Keywords | Field | DocType |
host computational capacity,nics proximity,o-aware design,high bandwidth network,o-aware last level,o cache,general cache,integrated nic,network speed,enhanced integrated nic,cache interference,multi-core processor,cache,simulator,multi core processor | Cache invalidation,Cache pollution,Computer science,Cache,Snoopy cache,Real-time computing,Cache algorithms,Page cache,Cache coloring,Smart Cache | Conference |
Citations | PageRank | References |
2 | 0.40 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guangdeng Liao | 1 | 263 | 13.94 |
| Laxmi N. Bhuyan | 2 | 2393 | 248.44 |
| Danhua Guo | 3 | 101 | 6.66 |
| Steve R King | 4 | 57 | 3.60 |