Title
The optimal wire order for low power CMOS
Abstract
If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.
Year
DOI
Venue
2005
10.1007/11556930_69
PATMOS
Keywords
Field
DocType
low power,geometric program,simple specific order,power optimization potential,new power optimal wire,representative circuit model,optimal wire order,promising result,previous approach,adjacent wire,power optimal wire spacing,power optimization
Power saving,Power optimization,Computer science,Electronic engineering,CMOS,Low-power electronics,Commutation
Conference
Volume
ISSN
ISBN
3728
0302-9743
3-540-29013-3
Citations 
PageRank 
References 
3
0.46
7
Authors
4
Name
Order
Citations
PageRank
Paul Zuber140.85
Peter Gritzmann241246.93
Michael Ritter371.25
Walter Stechele436552.77