Name
Title | ||
|---|---|---|
VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding |
Abstract | ||
|---|---|---|
An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm2 by a 0.6-μm triple-metal CMOS technology, processes a macroblock within 3.84 μs, and therefore is capable of decoding HDTV (1920×1152 pels) images in real time |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/76.473552 | IEEE Trans. Circuits Syst. Video Techn. |
Keywords | Field | DocType |
mpeg2 hdtv video decoding,high throughput,decoding hdtv,mpeg2 video decoder core,inverse discrete cosine transformer,high level,decoder core,motion compensator,different type,vlsi implementation,mpeg2 algorithm,main profile,very large scale integration,inverse problems,cmos technology,asynchronous transfer mode,videoconference,macroblock,motion compensation,video compression,vlsi,decoding | Computer science,Discrete cosine transform,Motion compensation,Electronic engineering,Artificial intelligence,Video decoder,Very-large-scale integration,Macroblock,Computer vision,High-definition television,CMOS,Decoding methods,Embedded system | Journal |
Volume | Issue | ISSN |
5 | 5 | 1051-8215 |
Citations | PageRank | References |
19 | 2.63 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Toshihiro Masaki | 1 | 83 | 12.30 |
| Y. Morimoto | 2 | 19 | 2.63 |
| T. Onoye | 3 | 37 | 10.36 |
| I. Shirakawa | 4 | 19 | 2.63 |