Paper Info
Title
DSP Code Generation with Optimized Data Word-Length Selection
Abstract
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application time-to-market, methodologies for automatically determining the fixed-point specification are required. In this paper, a new methodology for optimizing the fixed-point specification in the case of software implementation is described. Especially, the technique proposed to select the data word-length under a computation accuracy constraint is detailed. Indeed, the latest DSP generation allows to manipulate a wide range of data types through sub-word parallelism and multiple-precision instructions. In comparison with the existing methodologies, the DSP architecture is completely taken into account to optimize the execution time under accuracy constraint. Moreover, the computation accuracy evaluation is based on an analytical approach which allows to minimize the optimization time of the fixed-point specification. The experimental results underline the efficiency of our approach.
Year
DOI
Venue
2004
10.1007/978-3-540-30113-4_16
LECTURE NOTES IN COMPUTER SCIENCE
Keywords
Field
DocType
data type,digital signal processing,code generation,fixed point,fixed point arithmetic,embedded system
Signal processing,Digital signal processing,Computer science,Digital signal,Digital signal processor,Parallel computing,Data-flow analysis,Code generation,Data type,Word (computer architecture)
Conference
Volume
ISSN
Citations 
3199
0302-9743
2
PageRank 
References 
Authors
0.43
11
2
Name
Order
Citations
PageRank
Daniel Menard120719.00
Olivier Sentieys259773.35