Name
Abstract | ||
|---|---|---|
This paper presents the design and study of a circuit architecture able to perform 16Gbps GFP frame delineation with single bit error correction using UMC 130nm standard cell technology. The design targets the development of a hard macro core for the design of next generation network processing platforms. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISVLSI.2006.14 | ISVLSI |
Keywords | Field | DocType |
circuit architecture,gfp frame delineation,vlsi gfp frame delineation,hard macro core,single bit error correction,next generation network processing,standard cell technology,next generation network,polynomials,integrated circuit design,information technology,vlsi,synchronization,read only memory,payloads,cyclic redundancy check,error correction,very large scale integration | Synchronization,Read-only memory,Cyclic redundancy check,Computer science,Error detection and correction,Integrated circuit design,Standard cell,Macro,Computer hardware,Very-large-scale integration | Conference |
ISBN | Citations | PageRank |
0-7695-2533-4 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ciaran Toal | 1 | 28 | 6.99 |
| Sakir Sezer | 2 | 1010 | 84.22 |
| Xin Yang | 3 | 22 | 4.91 |