Title
A sigma-delta ADC with decimation and gain control function for a Bluetooth receiver in 130 nm digital CMOS
Abstract
We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architecture was chosen for antialiasing filtering. The decimation-by-two function is realized using divided-by-two clock signals in the antialiasing filter. Antialiasing, gain control, and sampling functions are merged in the sampling network using SC techniques. This compact architecture allows operating the preceding blocks at twice the ADC's clock frequency, thus improving the noise performance of the wireless receiver channel and relaxing settling requirements of the analog building blocks. The presented approach has been validated and incorporated in a commercial single-chip Bluetooth radio realized in a 1.5 V 130 nm digital CMOS process. The measured antialiasing filtering shows better than 75 dB suppression at the folding frequency band edge. A 67 dB dynamic range was measured with a sampling frequency of 37.5 MHz.
Year
DOI
Venue
2006
10.1155/WCN/2006/71249
EURASIP J. Wireless Comm. and Networking
Keywords
Field
DocType
clock frequency,sigma-delta adc,sampling function,sampling network,nm digital cmos,bluetooth receiver,antialiasing filter,sampling frequency,db suppression,folding frequency band edge,gain control function,sc technique,compact architecture,db dynamic range,gain control
Clock signal,Decimation,Computer science,Sampling (signal processing),Real-time computing,Switched capacitor,Analog-to-digital converter,Delta-sigma modulation,Electronic engineering,Automatic gain control,Clock rate,Embedded system
Journal
Volume
Issue
ISSN
2006
2
1687-1499
Citations 
PageRank 
References 
0
0.34
2
Authors
5
Name
Order
Citations
PageRank
Jinseok Koh114523.87
Gabriel Gomez261.77
Khurram Muhammad326945.83
R. Bogdan Staszewski400.34
Baher Haroun5349.20