Paper Info
Title
Research on deep RIE-based through-si-via micromachining for 3-D system-in-package integration
Abstract
This paper reports the designing/simulation and experimental investigation into the Deep RIE-based microfabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with various sections, especially those with tapered profile. The effectiveness of the simulator is verified with process trials. Optimal deposition parameters are obtained for conformal formation of insulation, barrier and seed layers for electro-plating via filling. Combined with additives, Periodic Pulse Reverse current plating is utilized for satisfying bottom-up blind-via filling. The research have laid firm groundwork for the demonstration of the prospect of 3-D packaging based microsystem integration, combining heterogeneous micro/nano devices with ICs, in consumer, industrial and defense electronics. © 2009 IEEE.
Year
DOI
Venue
2009
10.1109/NEMS.2009.5068533
4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, NEMS 2009
Keywords
Field
DocType
Bulk Micromachining, Deep Reactive Ion Etching (DRIE), Through-Si-Via (TSV), System-in-package(Sip), Three dimensional integration
System in package,Nanotechnology,Microsystem,Composite material,Bulk micromachining,Surface micromachining,Mechanical engineering,Electronic packaging,Deep reactive-ion etching,Electronics,Interconnection,Materials science
Conference
ISSN
Citations 
PageRank 
2474-3747
0
0.34
References 
Authors
0
7
Name
Order
Citations
PageRank
Miao Min1101.75
Jin Yufeng289.51
Liao Hongguang300.34
Liwei Zhao441235.79
yunhui501.35
Sun Xin600.68
Guo Yunxia700.68