Paper Info
Title
Understanding metrics in logic synthesis for routability enhancement
Year
DOI
Venue
2003
10.1145/639929.639931
SLIP
Keywords
Field
DocType
routability enhancement,logic synthesis,circuits,decomposition,layout,vlsi,structure,optimization
Logic synthesis,Computer architecture,Computer science,Logic optimization,Electronic engineering,Electronic circuit,Very-large-scale integration
Conference
ISBN
Citations 
PageRank 
1-58113-627-7
7
0.50
References 
Authors
11
2
Name
Order
Citations
PageRank
Victor N. Kravets112411.78
Prabhakar Kudva243856.96