Paper Info
Title
The irregular Z-buffer: Hardware acceleration for irregular data structures
Abstract
The classical Z-buffer visibility algorithm samples a scene at regularly spaced points on an image plane. Previously, we introduced an extension of this algorithm called the irregular Z-buffer that permits sampling of the scene from arbitrary points on the image plane. These sample points are stored in a two-dimensional spatial data structure. Here we present a set of architectural enhancements to the classical Z-buffer acceleration hardware which supports efficient execution of the irregular Z-buffer. These enhancements enable efficient parallel construction and query of certain irregular data structures, including the grid of linked lists used by our algorithm. The enhancements include flexible atomic read-modify-write units located near the memory controller, an internal routing network between these units and the fragment processors, and a MIMD fragment processor design. We simulate the performance of this new architecture and demonstrate that it can be used to render high-quality shadows in geometrically complex scenes at interactive frame rates. We also discuss other uses of the irregular Z-buffer algorithm and the implications of our architectural changes in the design of chip-multiprocessors.
Year
DOI
Venue
2005
10.1145/1095878.1095889
ACM Trans. Graph.
Keywords
DocType
Volume
image plane,architectural change,hardware acceleration,architecture,irregular Z-buffer algorithm,classical Z-buffer acceleration hardware,classical Z-buffer visibility algorithm,irregular Z-buffer,real-time graphics hardware,visible surface algorithms,shadow algorithms,MIMD fragment processor design,architectural enhancement,efficient execution,computer graphics,certain irregular data structure
Journal
24
Issue
ISSN
Citations 
4
0730-0301
40
PageRank 
References 
Authors
2.75
23
4
Name
Order
Citations
PageRank
Gregory S. Johnson11597.92
Juhyun Lee2819.99
Christopher A. Burns3694.18
William R. Mark41342156.73