Paper Info
Title
A sub-2W 10GBase-T analog front-end in 40nm CMOS process
Abstract
The IEEE802.3an 10GBase-T standard [1] provides full duplex transmission and reception over 4 twisted pairs in a 100M UTP cable. Earlier AFE implementations for this standard have utilized a transmitter hybrid configuration requiring multiple DACs with stringent inter-DAC matching requirements [2-3]. This paper describes a new AFE architecture using a single DAC and line-driver to achieve better echo-cancellation linearity. The design achieves >;59dB TX SFDR and >;68dB echo-cancellation (EC) SFDR across 400MHz bandwidth. The AFE receiver circuitry consists of PGA and 2× time-interleaved SHA-less 11b pipelined ADC operating at 800MS/s. Measured receive noise floor and SFDR is <;-144dBm/Hz and >;53dB, respectively. The AFE dissipates less than 2W power, occupies 17mm2 silicon area including 4 lanes with clocking circuitry, and is implemented in a 40nm triple-gate 0.9V/1.2V/2.5V CMOS process.
Year
DOI
Venue
2012
10.1109/ISSCC.2012.6177068
Solid-State Circuits Conference Digest of Technical Papers
Keywords
Field
DocType
CMOS analogue integrated circuits,echo suppression,twisted pair cables,AFE implementations,AFE receiver circuitry,CMOS process,UTP cable,clocking circuitry,echo-cancellation linearity,full duplex transmission,line-driver,single DAC,size 40 nm,sub-2W 10GBase-T analog front-end,transmitter hybrid configuration
Transmitter,Twisted pair,Noise floor,Computer science,Analog front-end,Linearity,Spurious-free dynamic range,Electronic engineering,CMOS,Electrical engineering,Duplex (telecommunications)
Conference
ISSN
ISBN
Citations 
0193-6530
978-1-4673-0376-7
2
PageRank 
References 
Authors
0.56
4
10
Name
Order
Citations
PageRank
Tarun Gupta172.08
Frank Yang2132.52
Dong Wang320.56
Ali Tabatabaei420.56
Ramesh Singh520.56
Hesam Amir Aslanzadeh6113.89
Alireza Khalili720.56
Saurabh Vats830.90
Susan Arno951.46
Sean Campeau1020.56