Name
Abstract | ||
|---|---|---|
In this paper, we report the reduction in the base-collector capacitance (C-BC) of InP/InGaAs double heterojunction bipolar transistors with buried SiO2 wires (BG-HBT). In a previous trial, we could not confirm a clear difference between the C-BC of the conventional HBT and that of the BG-HBT because the subcollector layer was thicker than expected. In this study, the interface between the collector and the subcollector was shifted to the middle of the SiO2 wires by adjusting the growth temperature, and a reduction in C-BC with buried SiO2 wires was confirmed. The estimated C-BC of the BG-HBT was 7.6 fF, while that of the conventional HBT was 8.6 fF. This 12% reduction was in agreement with the 10% reduction calculated according to the designed size. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.917 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
heterojunction bipolar transistor MP, base-collector capacitance, in situ etching | Journal | E95C |
Issue | ISSN | Citations |
5 | 1745-1353 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoaki Takebe | 1 | 0 | 0.68 |
| Yasuyuki Miyamoto | 2 | 1 | 4.68 |