Name
Abstract | ||
|---|---|---|
In this paper, we extend our generalized methodology for designing lower-error area-efficient fixed-width two's-complement multipliers that receive two s-bit numbers and produce an s-bit product. The generalized methodology involving four steps results in several better error-compensation biases. These better error-compensation biases can be easily mapped to lower-error fixed-width multipliers suitable for VLSI realization. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ISCAS.2002.1009778 | ISCAS (1) |
Keywords | Field | DocType |
lower-error area-efficient fixed-width multipliers,s-bit numbers,multiplying circuits,error-compensation biases,digital arithmetic,two's-complement multipliers,vlsi,s-bit product,hardware | Computer science,Arithmetic,Electronic engineering,Very-large-scale integration | Conference |
Volume | Citations | PageRank |
1 | 2 | 0.77 |
References | Authors | |
2 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lan-Da Van | 1 | 179 | 31.46 |
| Sung-huang Lee | 2 | 2 | 1.10 |