Title
A High Performance Router Architecture for Interconnection Networks
Abstract
In this paper, we propose a new router architecture that supports wormhole switching and circuit switching concurrently. This architecture has been de- signed to take advantage of temporal communication loc- ality. This can be done by establishing a circuit between nodes that are going to communicate frequently. Messages using those circuits face no contention. By combining cir- cuit switching, pre-established physical circuits and wav e pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre-established phys- ical circuits. This router architecture also allows to redu ce the overhead of the software messaging layer in multicom- puters by offering a better hardware support. Preliminary performance evaluation results show a drastic reduction in latency and increment in throughput when messages are long enough, even if circuits are established for a single transmission and locality is not exploited.
Year
DOI
Venue
1996
10.1109/ICPP.1996.537144
ICPP, Vol. 1
Keywords
Field
DocType
circuit switched,switches,message passing,hardware,bandwidth,circuit switching,computer architecture,throughput
Pipeline (computing),Circuit switching,Wormhole switching,Computer science,Latency (engineering),Parallel computing,Computer network,Bandwidth (signal processing),Throughput,Electronic circuit,One-armed router
Conference
Citations 
PageRank 
References 
35
3.84
14
Authors
4
Name
Order
Citations
PageRank
José Duato13481294.85
Pedro López263964.48
Federico Silla357656.77
Sudhakar Yalamanchili41836184.95