Name
Abstract | ||
|---|---|---|
Parallel counters (unary-to-binary converters) are the principal component of a Dadda multiplier. We specify a design first for a pipelined parallel counter, and then for a complete multiplier. As a result of its structural regularity, the layout is suitable for use in a VLSI implementation. We analyze the complexity of the resulting design using a VLSI model of computation, showing that it is optimal with respect to both its period and latency. In this sense the design compares favorably with other recent VLSI multiplier designs. |
Year | DOI | Venue |
|---|---|---|
1983 | 10.1145/357360.357366 | ACM Trans. Comput. Syst. |
Keywords | Field | DocType |
pipelined dadda multiplier,complexity,layout,vlsi,multiplier,vlsi layout,principal component,model of computation | Computer architecture,Computer science,Parallel processing,Arithmetic,Converters,Multiplier (economics),Model of computation,Electronic circuit,Very-large-scale integration,Integrated circuit,Vlsi layout,Distributed computing | Journal |
Volume | Issue | ISSN |
1 | 2 | 0734-2071 |
Citations | PageRank | References |
25 | 6.94 | 14 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter R. Cappello | 1 | 389 | 60.01 |
| Kenneth Steiglitz | 2 | 1128 | 660.13 |