Name
Abstract | ||
|---|---|---|
With the constantly increasing gate capacity of FP- GAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, Network- On-Chip (NoC), in which different flows share a point-to-point link, becomes advantageous in terms of scalability. Although fixed regular network infrastructures are only used in recent FPGA- based NoCs, the network topology can be optimized to fit the target application on FPGAs. In this paper, we investigate the suitable interconnects based on the typical implementation of NoC router with various number of wires per channel on FPGAs. In order to clearly illustrate the trade-off between network throughput and hardware amount for network components, we evaluate the amount of hardware for various networks, which are composed by routers with different port numbers, and their throughput using a flit- level simulation. Evaluation results show that for small systems with 16 cores or less, a large router is advantageous from the viewpoint of both performance and cost. On the other hand, when systems become large, the partitioned networks are efficient from the viewpoint of cost. |
Year | Venue | Keywords |
|---|---|---|
2006 | ERSA | network-on-chip,router,sim- ulation i. introduction,fpga,node degree,network on chip |
Field | DocType | Citations |
Computer architecture,Computer science,Field-programmable gate array,Parametric statistics,Scalability | Conference | 6 |
PageRank | References | Authors |
0.57 | 12 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daihan Wang | 1 | 82 | 4.78 |
| Hiroki Matsutani | 2 | 576 | 62.07 |
| Masato Yoshimi | 3 | 106 | 22.49 |
| Michihiro Koibuchi | 4 | 726 | 74.68 |
| Hideharu Amano | 5 | 1375 | 210.21 |