Paper Info
Title
Efficient ASIP design for configurable processors with fine-grained resource sharing
Abstract
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases
Year
DOI
Venue
2008
10.1145/1344671.1344687
FPGA
Keywords
Field
DocType
exploration space,efficient asip design,identical portion,asip design automation flow,fine-grained resource sharing,different custom instruction,area constraint,custom instruction,embedded application,configurable processor,execution speed,application-specific instruction-set processors,resource sharing,design,performance,computer architecture,register file,design automation,application specific instruction set processor,algorithms
Computer science,Parallel computing,Register file,Embedded applications,Real-time computing,Electronic design automation,Heuristics,Custom instruction,Shared resource,Speedup,Embedded system
Conference
Citations 
PageRank 
References 
12
0.62
11
Authors
3
Name
Order
Citations
PageRank
Quang Dinh1465.69
Deming Chen21432127.66
Martin D. F. Wong33525363.70