Title
Algorithm for Communication Synchronization on Reconfigurable Processor Arrays with Faults
Abstract
Efficient fault tolerant techniques for reconfigurable multiprocessor array have been extensively studied to construct maximum target array from host array with faulty processors. Existing work focused on the reconfiguration algorithm without considering the communication synchronization of the target array. This paper proposes an algorithm to rearrange the long interconnects of the target array, in order to improve the communication performance in synchronization. In addition, divide and conquer strategy is utilized for deleting logical rows to form a high performance target array with given size. Experimental results show that the proposed algorithm achieves considerable improvement on communication performance in synchronization for the case of small fault rate which is often occurred in real applications.
Year
DOI
Venue
2012
10.1109/IPDPSW.2012.30
IPDPS Workshops
Keywords
Field
DocType
optimisation,logic circuits,target array,high performance target array,efficient fault tolerant technique,target array interconnects,host array,microprocessor chips,fault tolerant techniques,fault-tolerance,reconfiguration,reconfigurable architectures,fault tolerance,communication synchronization,communication performance,proposed algorithm,logical rows,reconfigurable multiprocessor array,maximum target array,faulty processors,reconfigurable processor arrays,synchronous optimization algorithm,reconfiguration algorithm,synchronisation,vlsi array,parallel processing,indexes,synchronization,very large scale integration
Logic gate,Sparse array,Synchronization,Computer science,Parallel computing,Algorithm,Multiprocessing,Fault tolerance,Divide and conquer algorithms,Very-large-scale integration,Control reconfiguration
Conference
ISSN
ISBN
Citations 
2164-7062
978-1-4673-0974-5
0
PageRank 
References 
Authors
0.34
12
4
Name
Order
Citations
PageRank
Wu Jigang176486.18
Guiyuan Jiang29621.05
Yuanrui Zhang318015.48
Yuanbo Zhu451.79