Name
Title | ||
|---|---|---|
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor |
Abstract | ||
|---|---|---|
A new parallel-processing wire-routing algorithm is presented and implemented on a parallel processor. The two main features of the parallel algorithm are the control of the path quality and the finding of a quasi-minimum Steiner tree. Both Lee's maze algorithm and the proposed algorithm are implemented on an AAP-1 two-dimensional array processor, and the performance is compared to that of software programming on a general-purpose computer. It is shown experimentally that routing by the proposed algorithm implemented on the AAP-1 is 230 times faster than a software maze router run on a 1-MIPS computer for a three-pin/net circuit on a 256 X 256 grid. |
Year | DOI | Venue |
|---|---|---|
1987 | 10.1109/TCAD.1987.1270268 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
software programming,parallel algorithm,maze algorithm,general-purpose computer,Parallel Adaptable Routing Algorithm,software maze router,AAP-1 two-dimensional array processor,proposed algorithm,Two-Dimensional Array Processor,parallel processor,new parallel-processing wire-routing algorithm,1-MIPS computer | Journal | 6 |
Issue | ISSN | Citations |
2 | 0278-0070 | 17 |
PageRank | References | Authors |
1.56 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| T. Watanabe | 1 | 252 | 51.28 |
| Kitazawa, H. | 2 | 17 | 1.90 |
| Sugiyama, Y. | 3 | 17 | 1.56 |