Abstract | ||
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This paper describes a compiler and algorithms for simulation and fault diagnosis of computer hardware modeled in VHSIC Hardware Description Language(VHDL). Given a VHDL description, the compiler creates an internal representation. For simulation, a discrete-event based compiled code simulation algorithm is used. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension. |
Year | DOI | Venue |
---|---|---|
1991 | 10.1145/127601.127647 | DAC |
Keywords | Field | DocType |
fault diagnosis,vhdl description,fault model,hardware,computational modeling,databases,first principle,computer simulation,application software,data structures,design automation | Permission,Data structure,Computer science,Software fault tolerance,Compiler,Real-time computing,Compiled language,Electronic design automation,VHDL,Computer engineering,Fault model | Conference |
ISBN | Citations | PageRank |
0-89791-395-7 | 5 | 0.48 |
References | Authors | |
8 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Vijay Pitchumani | 1 | 125 | 21.38 |
Pankaj Mayor | 2 | 9 | 1.30 |
Nimish Radia | 3 | 20 | 2.86 |