Title
A system for fault diagnosis and simulation of VHDL descriptions
Abstract
This paper describes a compiler and algorithms for simulation and fault diagnosis of computer hardware modeled in VHSIC Hardware Description Language(VHDL). Given a VHDL description, the compiler creates an internal representation. For simulation, a discrete-event based compiled code simulation algorithm is used. For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used. The diagnosis algorithm reasons from first principles using constraint suspension.
Year
DOI
Venue
1991
10.1145/127601.127647
DAC
Keywords
Field
DocType
fault diagnosis,vhdl description,fault model,hardware,computational modeling,databases,first principle,computer simulation,application software,data structures,design automation
Permission,Data structure,Computer science,Software fault tolerance,Compiler,Real-time computing,Compiled language,Electronic design automation,VHDL,Computer engineering,Fault model
Conference
ISBN
Citations 
PageRank 
0-89791-395-7
5
0.48
References 
Authors
8
3
Name
Order
Citations
PageRank
Vijay Pitchumani112521.38
Pankaj Mayor291.30
Nimish Radia3202.86