Paper Info
Title
A coarse-grained reconfigurable architecture with compilation for high performance
Abstract
We propose a fast data relay (FDR) mechanism to enhance existing CGRA (coarse-grained reconfigurable architecture). FDR can not only provide multicycle data transmission in concurrent with computations but also convert resource-demanding inter-processing-element global data accesses into local data accesses to avoid communication congestion. We also propose the supporting compiler techniques that can efficiently utilize the FDR feature to achieve higher performance for a variety of applications. Our results on FDR-based CGRA are compared with two other works in this field: ADRES and RCP. Experimental results for various multimedia applications show that FDR combined with the new compiler deliver up to 29% and 21% higher performance than ADRES and RCP, respectively.
Year
DOI
Venue
2012
10.1155/2012/163542
Int. J. Reconfig. Comp.
Keywords
Field
DocType
new compiler,inter-processing-element global data access,higher performance,fdr feature,local data access,high performance,multicycle data transmission,compiler technique,coarse-grained reconfigurable architecture,fdr-based cgra,fast data
Architecture,Data transmission,Computer science,Parallel computing,Compiler,Real-time computing,Relay,Embedded system,Computation
Journal
Volume
Citations 
PageRank 
2012,
1
0.36
References 
Authors
20
3
Name
Order
Citations
PageRank
Lu Wan11347.39
Chen Dong2352.99
Deming Chen31432127.66