Name
Title | ||
|---|---|---|
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates |
Abstract | ||
|---|---|---|
The opportunities created by modern microelectronic technology cannot effectively be exploited, because of weaknesses in traditional circuit synthesis methods used in today's CAD tools. In this paper, a new information-driven circuit synthesis method is discussed that targets combinational circuits implemented with gates. The synthesis method is based on our original information-driven approach to circuit synthesis, bottom-up general functional decomposition and theory of information relationship measures, and considerably differs from all other known methods. The discussion is focused on various sub-function construction methods used during the synthesis. The experimental results from the automatic circuit synthesis tool that implements the method show that the developed by us specific sub-function construction methods targeted to the gate-based circuits deliver much better circuits than the other methods and demonstrate that the information-driven general decomposition produces very fast and compact gate-based circuits. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DSD.2005.48 | digital systems design |
Keywords | Field | DocType |
high-quality sub-function construction,process variation,device count,vlsi chip increase,information-driven circuit synthesis,clock rate,costly problem,present level,spot defect,feature size | Cad tools,Microelectronics,Functional decomposition,Electronic engineering,Combinational logic,Engineering,Electronic circuit | Conference |
ISBN | Citations | PageRank |
0-7695-2433-8 | 0 | 0.34 |
References | Authors | |
15 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lech Jowiak | 1 | 1 | 0.82 |
| Szymon Bieganski | 2 | 1 | 1.06 |