Paper Info
Title
High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation
Abstract
In this paper a high-speed fading architecture that generates multiple stochastic processes based on the Sum-of-Sinusoids (SOS) method is presented. In the proposed architecture, the fading samples are generated according to either symmetrical or asymmetrical power spectral density (PSD) in an efficient FPGA-based architecture. This proposal allows the emulation of more realistic channels in non-isotropic environments. The sinusoid evaluation is performed by the piecewise polynomial approximation using processor arrays (PAs) technique in an efficient hardware-level structure. This technique offers the maximum possible parallelism, high accuracy in the generated samples, high frequency resolution as well as high rate sinusoid evaluation. The proposed architecture can be used to construct a flexible channel emulator for the current communication standards.
Year
DOI
Venue
2011
10.1109/ReConFig.2011.50
Reconfigurable Computing and FPGAs
Keywords
Field
DocType
channel emulation,asymmetrical power spectral density,high-speed fading architecture,high-speed stochastic processes generator,sinusoid evaluation,high frequency resolution,fading sample,efficient fpga-based architecture,efficient hardware-level structure,high rate sinusoid evaluation,high accuracy,proposed architecture,doppler effect,field programmable gate arrays,high frequency,computer architecture,stochastic process,polynomials,stochastic processes,fpga,generators,power spectral density,fading
Polynomial,Computer science,Fading,Field-programmable gate array,Stochastic process,Communication channel,Real-time computing,Emulation,Spectral density,Piecewise
Conference
ISBN
Citations 
PageRank 
978-1-4577-1734-5
0
0.34
References 
Authors
5
4
Name
Order
Citations
PageRank
L. R. Vela-Garcia100.34
J. Vazquez Castillo284.59
R. Parra-Michel3235.19
A. Castillo-Atoche4232.93