Name
Abstract | ||
|---|---|---|
In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISVLSI.2011.14 | ISVLSI |
Keywords | DocType | ISSN |
clock frequency,point arithmetic,encoder resource,traditional ac encoder,chaotic map,dsp slice,simultaneous coding,hardware implementation,decoder performance,virtex-6 fpga,chaotic maps,field programmable gate arrays,encryption,context modeling,fixed point arithmetic,coding,cryptography,fpga,arithmetic coding,encoding,hardware,decoding | Conference | 2159-3469 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amit Pande | 1 | 269 | 24.58 |
| Joseph Zambreno | 2 | 377 | 44.73 |
| Prasant Mohapatra | 3 | 4344 | 304.46 |