Paper Info
Title
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications
Abstract
We present an SoC-based cryptographic co-processor for server applications, which supports different public key cryptographic schemes. Its novel architecture comprises multiple cores and utilizes HW/SW co-design to support flexibility concerning the supported cryptographic schemes. The emphasis on servers shifts the focus to high throughput, while the usual metric in literature is low latency. Thus, to gain low latency, usual architectures feature high parallelization at the lowest abstraction level leading to some limitations regarding the throughput, if used to support different schemes. Consequently, the proposed architecture utilizes parallelization at this level only to a low degree and compensates the resulting loss in efficiency by heavily exploiting parallelization at higher abstraction levels.
Year
DOI
Venue
2008
10.1109/ISVLSI.2008.9
ISVLSI
Keywords
Field
DocType
high parallelization,low latency,high throughput,efficient server-based public key,different scheme,cryptographic applications,soc-based cryptographic co-processor,novel multiple core co-processor,proposed architecture utilizes parallelization,cryptographic scheme,different public key cryptographic,higher abstraction level,low degree,computer networks,public key,cryptography,throughput,servers,coprocessors,parallelization,field programmable gate arrays,multi core,public key cryptography,computer architecture,system on chip,application software,elliptic curve cryptography,soc,processor architecture
Computer science,Server,Throughput,Latency (engineering),Coprocessor,Application software,Abstraction layer,Multi-core processor,Public-key cryptography,Embedded system
Conference
ISBN
Citations 
PageRank 
978-0-7695-3170-0
2
0.41
References 
Authors
11
5
Name
Order
Citations
PageRank
Ralf Laue154242.64
H. Gregor Molter21086.83
Felix Rieder320.41
Sorin A. Huss425538.96
Kartik Saxena520.75