Name
Abstract | ||
|---|---|---|
As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost. However, these devices suffer from program performance degradation since tighter Vth distribution is required. On the other hand, area scaling is a candidate to achieve low cost while maintaining high program performance even though there are several hurdles to overcome, such as FG coupling and charge retention. As the cell size gets smaller, the Vth distribution widens and the erase-write cycling margin is decreased by the floating-gate coupling ratio. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746282 | ISSCC |
Keywords | DocType | ISSN |
NAND circuits,program performance degradation,memory size 32 GByte,erase-write cycling margin,margin-expanding scheme,CMOS,MLC NAND flash memory,CMOS memory circuits,flash memories,floating-gate coupling ratio | Conference | 0193-6530 |
ISBN | Citations | PageRank |
978-1-61284-303-2 | 0 | 0.34 |
References | Authors | |
0 | 16 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tae-Yun Kim | 1 | 2 | 2.20 |
| Sang-don Lee | 2 | 0 | 0.68 |
| Jinsu Park | 3 | 1 | 1.07 |
| Ho-youb Cho | 4 | 0 | 0.34 |
| Byoung-sung You | 5 | 0 | 0.34 |
| Kwang-ho Baek | 6 | 0 | 0.34 |
| Jae-Ho Lee | 7 | 202 | 42.11 |
| Chang-won Yang | 8 | 0 | 0.34 |
| Misun Yun | 9 | 0 | 0.34 |
| Minsu Kim | 10 | 414 | 64.12 |
| Jong Woo Kim | 11 | 317 | 34.45 |
| Eun-seong Jang | 12 | 0 | 0.34 |
| Hyun Chung | 13 | 1 | 0.74 |
| Sang-o Lim | 14 | 0 | 0.34 |
| Bong-Seok Han | 15 | 2 | 1.41 |
| Yo-Hwan Koh | 16 | 16 | 7.54 |