Title
A Versatile Hardware Architecture For A Cfar Detector Based On A Linear Insertion Sorter
Abstract
This paper presents a versatile hardware architecture that implements six variant of the CFAR detector based on linear and non-linear operations. Since some implemented CFAR detectors require sorting, a linear sorter based on a First In First Out (FIFO) schema is used The proposed architecture can be used as a specialized module or co-processor for Software Defined Radar (SDR) applications. The results of implementing the architecture on a Field Programmable Gate Array (FPGA) are presented and discussed.
Year
DOI
Venue
2008
10.1109/FPL.2008.4629985
2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2
Keywords
Field
DocType
noise,first in first out,field programmable gate array,radar,computer architecture,signal detection,detectors,linear operator,field programmable gate arrays,sorting,hardware architecture
Radar,FIFO (computing and electronics),Computer science,Field-programmable gate array,Sorting,FIFO and LIFO accounting,Software,Computer hardware,Detector,Embedded system,Hardware architecture
Conference
ISSN
Citations 
PageRank 
1946-1488
1
0.36
References 
Authors
3
4
Name
Order
Citations
PageRank
Roberto Perez-Andrade1395.88
René Cumplido217129.56
Claudia Feregrino Uribe37521.71
Fernando Martín del Campo4323.62