Name
Abstract | ||
|---|---|---|
With high clock frequencies, faster transistor rise/fall time, long signal wires, and the use of wider wires and Cu material interconnects, the interconnect inductance, and the noise generated because of this inductance, is becoming an important design metric in digital circuits. For a risk-free layout solution of a chip, capacitive and inductive noises should be considered at various routing process stages. A formulation and efficient solution for the min-area shield insertion problem to satisfy given explicit noise bounds in multiple coupled nets is provided. The noise model used can handle different wire widths, different spacing among wires, and different wire lengths. The model also is aware of the skin effect in high frequency ranges. Experimental results show that the proposed approach gives minimum number of shields to satisfy the noise constraints and uses less runtime than the best alternative approach. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/SBCCI.2003.1232838 | SBCCI |
Keywords | Field | DocType |
efficient solution,shield insertion,different spacing,noise constraint,explicit inductive noise reduction,noise model,noise,different wire length,high clock frequency,minimum-area shield insertion,dsm,different wire width,inductance,alternative approach,algorithms,inductive noise,explicit noise bound,high frequency,skin effect,satisfiability,integrated circuit layout,digital circuits,chip,noise reduction,shielding | Integrated circuit layout,Noise reduction,Digital electronics,Skin effect,Inductance,Computer science,Electronic engineering,Chip,Capacitive sensing,Transistor | Conference |
ISBN | Citations | PageRank |
0-7695-2009-X | 2 | 0.41 |
References | Authors | |
6 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohamed A. Elgamel | 1 | 64 | 9.44 |
| Magdy A. Bayoumi | 2 | 803 | 122.04 |