Paper Info
Title
Design and Implementation of Memory Pools for Embedded DSP
Abstract
Two sorts of pool memory are developed for the needs of programming reconfigurable embedded DSP applications. One-piece signal free list and first-fit police are used in the designed of equal size memory pool in which the search time of a free block is faster than c-runtime allocator. Based on two-level segregated fit algorithm, unequal size memory pool is implemented for the requirements of low fragmentation and bounded responded times. The boundary of memory block allocated can be four words aligned. For making the allocation polices adaptable to various DSP hardware resource and DSP applications, a reusable software framework used for management of memory pools is presented. Pattern and bridge design pattern are used in the designing of frame Strategy work. The memory allocation algorithm can be selected according to DSP application and DSP memory resources. As a result, DSP embedded system developers can create multiple allocators for a signal complex application. The software framework and the algorithm are applied forADTS101 DSP hardware platform.
Year
DOI
Venue
2008
10.1109/CSSE.2008.1273
CSSE (2)
Keywords
Field
DocType
pool memory,memory pool,memory allocation algorithm,dsp application,foradts101 dsp hardware platform,equal size memory pool,dsp memory resource,memory block,memory pools,unequal size memory pool,dsp embedded system developer,resource management,bridge design pattern,memory management,embedded systems,memory allocation,dynamic memory allocation,software framework,design pattern,algorithm design and analysis,real time operating system,digital signal processing,real time systems,embedded system
Registered memory,Free list,Interleaved memory,Computer science,Memory pool,Memory management,Texas Instruments DaVinci,Memory map,Allocator,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
3
Authors
2
Name
Order
Citations
PageRank
Xi-min Wang100.68
Zhe Wang23413.41